Digital Voice Systems VC-20-ATC-10B Dokumentacja Pobierz pdf (Strona 13)

FAA20 Embedded NEXCOM Vocoder

Board Manual

This manual has been prepared for the Federal Aviation Administration.

FA100-00107 (March 2004) – Rev 1.0.0 Page 7

SIGNAL PIN DIR DESCRIPTION

DR B11 I Serial Receive Data: Linear 16-bit PCM voice is input to

the FAA20 at a rate of 8000 samples/second. Each

sample is received serially (MSB first) beginning with the

falling edge of the SCLK after the FSR signal is detected.

SCLK B9 I/O Serial Shift Clock: The serial shift clock transfers transmit

and receive serial data. Transmit data is output on the

rising edge of clock. Receive data is sampled on the

falling edge of clock.

FSX B7 I/O Serial Transmit Frame Sync (active high): The FAA20

samples this signal on the falling edge of SCLK. An

active signal begins the transfer of Transmit Data. The

FSX signal should be asserted for only one bit period at a

rate of 8 kHz.

FSR B12 I/O Serial Receive Frame Sync (active high): The FAA20

samples this signal on the falling edge of SCLK. An

active signal begins the transfer of Receive Data. The

FSR signal should be asserted for only one bit period at a

rate of 8 kHz.

SPRDY C7 O Serial Port Ready Status: Unlike the VC-20, the FAA20

serial port is dedicated to serial port transfers and is

always ready. This signal is tied to +5V with a pull up

resistor to insure compatibility with VC-20

implementations.

CONTROL/STATUS SIGNALS

RUN A6 O Run Status (active high): The FAA20 asserts this signal

when it actively encoding or decoding voice. The signal

is synchronous with ECLK. The FAA20 also lights LED6

when encoding or decoding; however, the LED6 state

changes are driven by the FAA20 DSP and are not

synchronous with ECLK.

Note: This bit is not functional in TEST mode.

RESX A7 O Reset Status (active low): The FAA20 asserts this signal

when reset is active. The signal is driven by the FAA20

hardware signal state and not driven by the FAA20 DSP

software. The FAA20 is reset under any of the following

conditions: power up, RSTI assertion, and/or FAA20

watchdog timeout.

DINRS A15 I Reset Signal (active high): The reset signal can be

externally asserted to reset the FAA20. An active signal

with a minimum duration of 300 ns resets the board. A

built-in pull-up resister disables this signal when the pin is

left unconnected.

ECHO A23 I

rsvd

Echo Canceller Enable (active low): The FAA20 does not

include a built-in echo canceller. The FAA20 software

ignores this signal. A built-in pull-up resister disables this

signal when the pin is left unconnected.

VAD A22 I Voice Detection Enable (active low): This signal must be

asserted to enable FAA20 voice/silence detection and

comfort noise generation. This signal is sampled on the

falling edge of DCLK. A built-in pull-up resister disables

this signal when the pin is left unconnected.

Note: This bit is not functional in TEST mode.

DDET A17 O

rsvd

DTMF Detection Status (active high): This signal is not

used by the FAA20. During power up, it is initialized to

the low (inactive) state.

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